1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device including grooves in which semiconductor fillers are placed.
2. Description of the Related Art
FIG. 37 is a plan view showing a diffusion structure of a conventional semiconductor device 101. This plan view corresponds to a cross section of a semiconductor substrate taken along a plane which is across a source region described below and is parallel to a surface of the semiconductor substrate.
FIG. 38 is a sectional view taken along the line J—J in FIG. 37, and FIG. 39 is a sectional view taken along the line K—K in FIG. 37. On the contrary, FIG. 37 corresponds to a sectional view taken along the line S—S in each of FIG. 38 and FIG. 39.
The semiconductor device 101 includes a semiconductor substrate 110. The semiconductor substrate 110 includes a semiconductor layer 111 and a low concentration layer 112 formed on the semiconductor layer 111. The semiconductor layer 111 is made of silicon single crystal doped with an N+-type impurity at a high concentration. The low concentration layer 112 is formed of an N−-type silicon epitaxial layer.
A plurality of semiconductor chip patterns described below are formed in a regular manner on the above-described semiconductor substrate 110. When the semiconductor substrate 110 is cut so as to separate individual chips from each other, the semiconductor device 101 described below can be obtained for each of the cut portions.
The semiconductor device 101 is now described. The semiconductor device 101 is a quadrangular semiconductor chip in a cut state. In its central portion, an active region, on which a trench-type power MOSFET described below is placed, is provided.
In the active region, a plurality of narrow active grooves 1221 to 1224 are placed so as to be parallel to each other.
In the periphery of the active region, a quadrangular ring-shaped inner circumferential groove 130 is provided so as to surround the active grooves 1221 to 1224, but not to be in contact with each of the active grooves 1221 to 1224. Moreover, in the periphery of the active region, a plurality of quadrangular ring-shaped guard ring grooves 1231 to 1233 are placed so as to surround the inner circumferential groove 130. The guard ring grooves 1231 to 1233 and the inner circumferential groove 130 concentrically surround the active grooves 1221 to 1224.
A P-type semiconductor filler 125 is placed in each of the grooves 1221 to 1224, 130, and 1231 to 1233.
Upper portions of the semiconductor fillers 125 in the active grooves 1221 to 1224 are removed. On the side face of the removed portion of each of the active grooves 1221 to 1224, a gate insulating film 151 is formed. The remaining parts of the semiconductor fillers 125 in the active grooves 1221 to 1224 are situated below the gate insulating film 151.
Gate electrode plugs 155 made of polysilicon are formed on the surfaces of the gate insulating films 151. In each of the active grooves 1221 to 1224, a part surrounded by the gate insulating film 151 is filled with each of the gate electrode plugs 155.
The gate electrode plugs 155 are connected to each other through a gate wiring made of a metal thin film not shown in the drawing.
A P-type base region 133 and an N-type source region 166 formed inside the base region 133 are placed between the active grooves 1221 to 1224 where at least one side of the central portion of each of the active grooves 1221 to 1224 in its longitudinal direction. In the vicinity of the surface of the semiconductor substrate 110, the source region 166 is in contact with the gate insulating film 151. At a position below the source region 166, the base region 133 is in contact with the gate insulating film 151.
A P-type ohmic region 165 having a higher concentration than that of the base region 133 is placed between the source regions 166 in the vicinity of the surface inside the base region 133.
A source electrode film 167 made of a metal thin film is formed on the surfaces of the source regions 166 and the surfaces of the ohmic regions 165 so as to be in contact therewith. A thermal oxide film 158 and a PSG film 163 are placed on each of the gate electrode plugs 155. The source electrode film 167 and the gate electrode plugs 155 are electrically insulated each other by the thermal oxide film 158 and the PSG film 163.
On the back face side of the semiconductor substrate 110, the surface of the semiconductor layer 111 is situated. On the surface of the semiconductor layer 111, a drain electrode film 170 is formed.
In the thus constituted semiconductor device 101, a positive voltage equal to or higher than a threshold voltage is applied to each of the gate electrode plugs 155 in the state where the source electrode film 167 is connected to a ground potential while a positive voltage is being applied to the drain electrode film 170. Then, an N-type inversion layer is formed in a channel region constituted by the interface between the base region 133 and the gate insulating film 151. As a result, the source region 166 and the low concentration layer 112 are connected to each other through the inversion layer, so that a current flows from the low concentration layer 112 toward the source regions 166.
In such a state, when the potential of each of the gate electrode plugs 155 is set at the same potential as that of the source electrode film 167, the inversion layer disappears so that current is not flowed. Under this condition, the transistor 101 is in a cutoff state.
When the semiconductor device 101 is in a cutoff state, a PN junction at the interface between the base region 133 and the low concentration layer 112 is reverse biased. As a result, a depletion layer is mainly expanded into the low concentration layer 112.
The semiconductor fillers 125 positioned on the bottoms of the active grooves 1221 to 1224 and the semiconductor fillers 125 positioned in the inner circumferential groove 130, and the guard ring grooves 1231 to 1233 are not in contact with each other and are respectively at a floating potential. When the reverse bias is increased so that the depletion layer reaches the semiconductor fillers 125, the depletion layer is also expanded from the semiconductor fillers 125.
When a reverse bias larger than the previously applied voltage is applied after the low concentration layer 112 between the active grooves 1221 to 1224 is entirely depleted, the depletion layer is uniformly expanded toward the semiconductor layer 111. Therefore, the semiconductor device 101 with a high withstanding voltage can be obtained.
In the semiconductor device 101 as described above, the semiconductor fillers 125 are formed by epitaxially growing semiconductor single crystal having the opposite conductivity type to that of the low concentration layer 112. However, since the semiconductor fillers 125 grow slower on both ends of the active grooves 1221 to 1224 than in their central portions, the heights of the semiconductor filler 125 are not uniform.
As a result, these uneven heights cause the short circuit between the gate electrode plug 155 and the low concentration layer 112 on both ends of the active grooves 1221 to 1224 or the current concentration on both ends of the active grooves 1221 to 1224, thereby adversely lowering a yield rate.